1. Field of the Invention
The present invention relates generally to a dynamic random access memory (DRAM) being operated at a low power-supply voltage. More particularly, it relates to a bit line sense-amplifier for amplifying the electric charge which first amplifies a cell charge applied to a bit line with a sufficient potential difference, prior to sensing the cell charge in a bit line sense-amplifier, thereby stably and quickly performing a sensing operation.
2. Description of the Related Art
Generally, as a degree of integration of DRAM increases, an internal power-supply voltage becomes lowered so as to reduce the power-consumption and to ensure a reliability of the memory element. The following table shows a tendency in the power-supply voltage being used in the integration of each DRAM.
DRAM 64 Mb 256 Mb 1 Gb over 4 Gb integration degree power-supply 3.3 V 2.5 V 1.5 V below 1.2 voltage
Therefore, in order to use a low power-supply voltage and to reduce the size of a chip, the number of cells connected to a bit line becomes increased in the new DRAM. Accordingly, a bit line signal's voltage being generated when a cell charge is transmitted to the bit line becomes lowered.
Even if a bit line signal ranges from 200 mV to 300 mV in a conventional DRAM, the bit line signal is reduced to about 100 mV in a gigabit DRAM. If the bit line signal is too low, a stable operation is not assured by an offset voltage of a sense-amplifier. Also, a high-speed operation is limited.
In the present invention, the electric charge stored in a cell capacitor is transmitted to a bit line in order to generate a bit line signal in an electric charge amplifier, and a sense-amplifier is operated after amplifying this bit line signal, thereby performing a stable and rapid sensing operation. Therefore, the present invention relates to a bit line sense-amplifier suitable to a memory operated at a low voltage.
In a DRAM memory using a cell having one transistor and one capacitor, a bit line signal (AVBL) can be obtained by the following equations. EQU Assumption: VBLP=Vdd/2, EQU .beta.=CBL/CS (capacitance ratio), EQU .DELTA.VBL=(Vdd/2).times.(1/1+.beta.)
As known from the above equations, the bit line signal is determined by a power-supply voltage Vdd and the capacitance ratio .beta.. Accordingly, since a power-supply voltage Vdd is at a low value in a DRAM of low voltage, the capacitance ratio .beta. should be lowered to maintain a magnitude of the original bit line signal.
In cases that the number of cells connected to a bit line remains the same evwn with the increase of the integration degree of DRAM, a cell capacitance Cs is between 20-25 fF with no change and a bit line capacitance CBL is lowered by a scaling. Thus a bit line signal's magnitude is maintained.
However, to reduce a size of a chip in a high integration DRAM, the number of cells connected to a bit line should be increased, so that a bit line signal becomes lowered as the power-supply voltage goes into a scaling down.
If the bit line signal is too low, it is difficult to make a stable sensing operation by an offset voltage of a bit line sense-amplifier. Furthermore, sensing speed is also reduced.
FIG. 1 is a circuit diagram of a conventional bit line sense-amplifier. If an electric charge stored in a cell capacitor CS is applied to a bit line by an actuation of a word line WLi(1.ltoreq.i.ltoreq.n), a voltage difference of a bit line signal .DELTA.VBL occurs between bit lines BL and /BL. After a predetermined time, a signal SAP is to be a voltage Vdd, and a signal SAN is to be a voltage Vss, so that a sensing and rewriting operations are performed. In case of a precharging operation, a bit line equalization signal BLEQ is actuated, thereby the bit lines are precharged with a bit line precharge voltage VBLP. Since the conventional bit line sense-amplifier senses a bit line signal as it is, it may occur a malfunction at a low bit line signal.